(1) Field of the Invention
The present invention relates to a bus bridge, and more particularly, it relates to an error avoiding technique in a bus bridge in which, for example, a delayed transaction is used.
(2) Description of the Related Art
In a computer system, available as one of broadly accepted local buses for connecting various input/output devices is a PCI (peripheral component interconnect) bus. Specifications of the PCI bus are described in PCI Local Bus Specification issued by PCISIC (Special Interest Group), which disclosure is hereby incorporated by reference. Because of the presence of the electrical restrictions in the PCI bus, only about four to five devices can be connected to one bus in an actual system. On the other hand, a small-sized computer (so-called personal computer) having the PCI bus is beyond personal use and increasingly applied to a large-sized system. Accordingly, there have arisen demands for the mounting of multiple SCSI (small computer systems interface) cards, network cards or the like for connecting a disc device. For example, a PCI-to-PCI bridge meets such a demand.
According to the PCI-to-PCI bridge, the originally existing PCI bus (hereinafter referred to as "the primary PCI bus") is expanded. Thereby, an electrically separated PCI bus of one lower class (hereinafter referred to as "the secondary PCI bus") can be obtained. Specifications of a conventional PCI-to-PCI bridge are described in PCI-to-PCI Bridge Architecture Specification issued by said PCISIG, which disclosure is hereby incorporated by reference.
FIG. 4 is a block diagram showing an example of a computer system in which the PCI-to-PCI bridge is used. In a computer system 1 shown in FIG. 4, a CPU 2 is connected via a CPU bus 3 to a host bridge 5 and a main memory 4 including a memory controller and a memory. The host bridge 5 functions as one bus master of a primary PCI bus 6. Other bus masters such as an ISA/EISA bridge 7, an SCSI controller 8, a network controller 9 and a PCI-to-PCI bridge 10 are connected to the primary PCI bus 6. To expand the primary PCI bus 6, a secondary PCI bus 11 providing four slots is further connected to the PCI-to-PCI bridge 10. To two of the slots there are connected an SCSI controller 13, to which a disc memory 12 is connected, and an SCSI controller 15, to which a tape device 14 is connected. Specifically, in the computer system 1 shown in FIG. 4, by connecting the secondary PCI bus 11 via the PCI-to-PCI bridge 10 to one slot of the primary PCI bus 6, the primary PCI bus 6 is expanded and the number of devices connectable to the entire system is increased.
Next, the operation of the above-mentioned conventional PCI-to-PCI bridge 10 will be described. There are two types of forwarding (system of transferring a bus transaction from an initiator bus to a target bus) of a bus transaction by the PCI-to-PCI bridge 10. In one system, as shown in a timing chart of FIG. 5, the initiator bus is occupied until the transaction of the target bus is completed. This is herein referred to as the non-delayed transaction. In the other system, as shown in a timing chart of FIG. 6, after a transaction is issued on the target bus, the initiator bus is temporarily opened. This is referred to as the delayed transaction. The delayed transaction is a function added from Revision 2.1 of said PCI Local Bus Specification, which disclosure is hereby incorporated by reference. An object of the function is to raise the bus operation efficiency and enhance the system performance.
Here, the non-delayed transaction and the delayed transaction will be described in more detail. FIG. 5 is a timing chart showing an example of an operation in which the non-delayed transaction is used and the CPU of FIG. 4 reads data of one word from a register of the SCSI controller 13. In this case, the host bridge 5 as the bus master first issues an IO read transaction 16 on the primary PCI bus 6. The PCI-to-PCI bridge 10 receives the IO read transaction 16 to perform a predetermined address conversion and so on. The corresponding IO read transaction 17 is issued on the secondary PCI bus 11 three clocks behind the rising of the IO read transaction 16. Then, target data is read from the register in the SCSI controller 13 at the timing of a final clock of the IO read transaction 17. The read data is temporarily stored in a buffer memory in the PCI-to-PCI bridge 10. Thereafter, two clocks later, the data is transmitted onto the primary PCI bus 6.
As seen from FIG. 5, in the non-delayed transaction, the primary PCI bus 6 is occupied by the IO read transaction for a period of eleven clocks. During this period, the other PCI devices cannot operate. Therefore, the PCI bus cannot be operated efficiently.
Next, an example of the operation of the computer system 1 in which the delayed transaction is used for processing the transaction in the PCI-to-PCI bridge 10 will be described. FIG. 6 is a timing chart showing an example of operation in which the CPU 2 of FIG. 4 reads the data of one word from the register in the SCSI controller 13. Here, an IO read transaction 18 issued on the primary PCI bus 6 is transferred via the PCI-to-PCI bridge 10 to the secondary PCI bus 11. At this time, the PCI-to-PCI bridge 10 transmits a control signal to the primary PCI bus 6 to release the primary PCI bus 6 before the target data is transferred to the primary PCI bus 6. On the other hand, on the secondary PCI bus 11, an IO read transaction 19 is issued and the register is read similar to in FIG. 5. The read target data is then stored in the buffer memory in the PCI-to-PCI bridge 10. Thereafter, an IO read transaction 20 is reissued on the primary PCI bus 6 for the same address. At this time, if there is data in the buffer memory, the data is transmitted to the primary PCI bus 6 at the third clock after the rising of the IO read transaction 20. The transaction is then completely ended.
In the delayed transaction shown in FIG. 6, for one IO read transaction, the primary PCI bus 6 is occupied for a period of six (=3+3) clocks. On the other hand, in the non-delayed transaction shown in FIG. 5, the period is eleven clocks. In this case, in the PCI-to-PCI bridge 10, by using the delayed transaction, the bus operation efficiency can be enhanced.
However, when the delayed transaction is used for processing the transaction in the PCI-to-PCI bridge 10, one problem occurs. FIG. 7 is a timing chart showing a defect occurring in the PCI-to-PCI bridge 10 in which the delayed transaction is used. In the computer system 1 shown in FIG. 4, the SCSI controller 13 reads a series of data from the disc memory 12, and finishes transferring the data to the primary PCI bus 6 as the host bus. An interrupt signal indicative of the completion of transfer is then transmitted toward the primary PCI bus 6. Subsequently, the CPU 2 responds to the interrupt signal, reissues an IO read transaction on the primary PCI bus 6 and reads a status register in the SCSI controller.
That is to say, the SCSI controller or the like is provided with the status register. When an interrupt signal is transmitted to the primary PCI bus 6, information indicating that interrupt occurs and information indicating whether or not data transfer is normally completed are stored in the status register. In many SCSI controllers, the content of the status register is cleared at the time of reading. This is done in an attempt to reduce the number of necessary processes for the SCSI controller.
FIG. 7 shows the defect accompanying the operation. The defect will be described with reference to the timing chart of FIG. 7. First, when an interrupt signal 23 is transmitted from the SCSI controller 13 to the secondary PCI bus 11, the interrupt signal 23 is read by CPU 2. The CPU 2 initiates a process for reading target data from the status register of the SCSI controller 13. First, an IO read transaction 21 is issued on the primary PCI bus 6. The transaction is processed by the PCI-to-PCI bridge 10 in the manner of a delayed transaction. If no data is stored in the buffer memory disposed in the PCI-to-PCI bridge 10, an IO read transaction 22 is issued on the secondary PCI bus 11. The valid data 23 is read from the status register. The read valid data 23 is held in the buffer memory of the PCI-to-PCI bridge 10 as valid read data 24. On the other hand, the content of the status register is cleared at the time it is read out as aforementioned, and changed into invalid data.
Furthermore, the read data 24 in the buffer memory of the PCI-to-PCI bridge 10 is not held permanently. If the read data 24 is not read from the primary PCI until after a predetermined time-out period T.sub.max elapses, it is discarded. It is described in said PCI Local Bus Specification Revision 2.1 that the time-out period T.sub.max corresponds to 2.sup.15 clocks at maximum. The time-out occurs when the computer system 1 frequently accesses other devices or continuously performs a network process to delay the timing at which the IO read transaction is reissued, or in some other cases.
After the data has been discarded because of the time-out, an IO read transaction 25 is reissued on the primary PCI bus 6. In this case, since no data resides in the buffer memory, the PCI-to-PCI bridge 10 again issues an IO read transaction 26 on the secondary PCI bus 11. Data is read again from the status register of the SCSI controller 13. However, at this time, the content of the status register of the SCSI controller 13 is already cleared and turned into the invalid data (refer to an arrow A). Therefore, invalid read data 27 is stored in the buffer memory of the PCI-to-PCI bridge. Thereafter, the invalid read data 27 is transmitted to the primary PCI bus 6 after an IO read transaction 28 which is issued on the primary PCI bus 6. The invalid data is decoded by the CPU 2. However, since the invalid data is different from an expected value, an error is caused in the CPU 2.
As aforementioned, when the computer system 1 is constructed by using the PCI-to-PCI bridge 10 in which the delayed transaction is used according to PCI Local Bus Specification Revision 2.1, data cannot be read normally from the device connected to the secondary PCI bus 11 in some cases. As a result, the reliability of the system is disadvantageously lowered.